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Features
* Besides the serial IEEE-1355 link, the T7906E provides several different interface
types: - Host interface The host interface provides 8 multiplexed data and address lines to program and control the T7906E locally - FIFO interface The FIFO interface provides the control signals FULL, WRITE, EMPTY and READ depending on the direction of the data flow (receive / transmit) - ADC interface The ADC interface allows to connect an ADC with a width of up to 16 bits directly to the T7906E - DAC interface The DAC interface provides up to 16 bits data lines and the required control signals. The data to be sent to the DAC are stored until a command "start DAC" is received - RAM interface The RAM interface provides a 16-bit data bus and a 16-bit address bus. Four chip select allow to address 4 different memory partitions. The memory interface can be programmed to use up to 7 wait states - UART interface Two independent UART interfaces are included. One UART uses dedicated I/O lines whereas the second UART is sharing its pins with the GPIO port - General purpose I/O This general Purpose Interface provides up to 24 bidirectional signal lines. The direction of each GPIO line can be set individually via register - Timer / Event Counter Two 32-Bit on-chip timers are available. Each timer provides a 32-Bit counter and a 32-Bit reload register. The two timers can be operated independently or cascaded - JTAG (IEEE 1149.1) For testing purposes, a standard IEEE 1149.1 interface is provided. It supports the JTAG function Bypass, Extest, Sample/preload, All-tristate and IDCode * Designed on Atmel MG1090E sea of gates matrix and packaged into MQFPF100 * Also called SMCS Lite (or SMCS116)
Single Point to Point IEEE 1355 High Speed Controller
T7906E
Description
The T7906E provides one IEEE-1355 serial communication link with 0 to 200 Mbit/s data transmit rate. It supports both the standard IEEE-1355 link protocol (transparent mode) as well as the header generation required for the enhanced transaction layer of the TSS901E. This protocol uses specific protocol headers that can be generated by the T7906E without requiring an external host controller. These headers are stored in specific header registers which allows headers with a length of 0 (equaling the transparent mode) to eight bytes per packet. Packetization of data sent by the T7906E over the link is also done automatically according to the settings of a packet length register. Another feature provided by the transaction layer supported by the T7906E is an automatic checksum generation on the link. This is generated and checked automatically by the T7906E without requiring support from a host or other external source. Errors on the link are flagged and a special error packet is sent over the link to signal the error condition. Programming the T7906E internal registers is done via the IEEE-1355 link. All internal registers are 8-bit wide addressable. Two simple commands (read and write) suffice to access all functions and registers of the T7906E.
Rev. A - 27-Aug.-01
1
T7906E
The interfaces of the T7906E such as the FIFO, UART, ADC/DAC and memory interface are accessed by a simple read or write operation to the corresponding interface address. In the case of FIFO, Host, UART and memory interface, a packet oriented access is also possible (meaning transferring multiple bytes with a single command). In case a communication memory is connected to the T7906E, this can be read and written to via the link specific registers. The IEEE-1355 links can support a range of communication speeds, which are programmed by writing to registers. At reset all links are configured to run at the base speed of 10 Mbits/sec. Only the transmission speed of a link is programmed as reception is asynchronous. This means that links running at different speeds can be connected, provided that each device is capable of receiving at the speed of the connected transmitter.
Introduction
Connecting a non-intelligent node to a processing element requires not only the communication controller, but usually a controlling instance for the communication circuitry. The latter has to be configured for settings like bit rate, packet sizes, handshake protocols etc. Should the non-intelligent node require remote control via commands, usually a second link, dedicated for commands is introduced. Using an IEEE-1355 link for that purpose eliminates the need for separate data and control paths, since the communication controller can differentiate between the two entities. In addition, it can be remotely configured, can execute simple commands and provides special I/O pins to control the interface unit. The T7906E provides one IEEE-1355 serial communication link together with additional features to support non-intelligent nodes as well as to control ADC and DAC converters. The T7906E is targeted at two main applications areas: * * Embedded systems Communication device for processor systems
Embedded systems
The main application targets of the T7906E are modules and units without any built-in communication features, such as special image compression chips, application specific programmable logic or mass memory. The T7906E is perfectly suited to be used on "non-intelligent" modules such as A/D-converter or sensor interfaces, due to its "control by link" feature and system control facilities. In addition, its fault tolerance feature make the device very interesting for many critical industrial measurement and control systems. Example applications of the T7906E as communication and system controller on an interface node consisting of an ADC and DAC and one where the T7906E is connected to four banks of memory are given in the figures below:
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Figure 1. Example applications
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T7906E
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T7906E
Communication device for microprocessors
Many applications require a link front end providing one link, but no controller instance on that unit. Due to the communication memory interface of the SMCSlite, it is also satisfying the requirements of these applications. Due to its small package and low power consumption it is an excellent alternative to FPGA based solutions. A system using the SMCSlite as a communication front-end for a microcontroller is shown in the figure below: Figure 2. Example application
Interfaces
FIFO interface The FIFO interface provides the control signals full, write, empty and read, depending on the direction of the data flow (receive/transmit). Data received from the FIFO interface is sent over the IEEE-1355 link grouped in packets. The length of a packet (in bytes) can be specified either by setting an internal counter or by external signals. This interface can be programmed to use 0 to 7 wait states. ADC/DAC interface The ADC interface allows to connect an ADC with a width of up to 16 bits directly to the T7906E. The AD conversion can be started by request via link or in a cyclic manner triggered by the on-chip timers. When the AD conversion is ready, this is recognized by an external signal like "ready" or by an internal trigger, for example from the on-chip timer. After reading the sample from the ADC it is then sent over the link. An 8-bit address generator is provided to allow multiplexing of analog signals. The address generator will start at a pre-programmed start address and will be incremented after each conversion. The DAC interface is very similar to the ADC interface. It provides up to 16 data lines and the required control signals. The data to be sent to the DAC is received from the link and is stored in a register until the command "start DAC" is received. After that command the register values will be put to the DAC.
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Block Diagram
5 8 2 2
JTAG
Internal control data bus
GPIO
UART
4
Link Interface
address/command bus
transmit/receive data bus
ADC I/F I/F Control Bus Data Bus
2
DAC I/F RAM I/F FIFO I/F
Internal Controller
28
12
Host Interface
Internal control bus & data control
system util.
Timer
2
16
Memory Interface The RAM interface provides a 16-bit data bus and 16-bit address bus. Four chip select lines allow to address four different memory partitions (banks). This partitioning into different banks is done using 4 internal address boundary registers. These are 8 bit wide and provide a minimum page size of 1024 words. The memory interface can be programmed to use 0 to 7 wait states. GPIO Interface The general purpose I/O (GPIO Interface) provides up to 24 bidirectional signal lines. The direction (input or output) of each GPIO line can be set individually via register. Data to/from the GPIO lines is written/read via the GPIO data register. The GPIO provides 8 dedicated I/O lines, the remaining 16 lines of the port are shared with the ADC address and host data bus. These GPIO lines are available when the corresponding unit (e.g. the host data bus) of the T7906Eis not being used (disabled). Two independent UARTs are included in the T7906E as well. One UART uses dedicated I/O lines whereas the second UART is sharing its pins with the GPIO port. The transmit rate of the UARTs in bps can be programmed via a 12-bit wide register with a maximum bit rate of about 780 kbit/s. The UARTs can optionally use hardware handshake (rts/cts). Although the T7906E is primarily designed to be remotely controlled, it can nevertheless be programmed and controlled by a local host if required. For that purpose a host interface provides 8 multiplexed data and address lines. Two 32-bit on-chip timers are available on the T7906E. Each timer provides a 32 bit counter and a 32 bit reload register. The two timers can be operated independently or
UART interface
Host Interface
Timers / Event Counter
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T7906E
cascaded. The timers can also be used to set an external signal when the timeout value is reached. Configuration After a chip reset the T7906E is configured by the internal controller. This can be either by receiving the configuration data from the IEEE-1355 link or by an external controller connected to the host port of the T7906E. Some of the functions of the T7906E presented above share the same I/O pins. This means, that some functions are mutually exclusive. As an example, the GPIO port shares some of its I/O pins with the host interface. If the host interface is not used, these pins are available for GPIO, otherwise they are used as the host address and data bus. The selection of which functions are being used is made by programming the appropriate registers after a chip reset. A short overview of the pin allocation and combinations of functions is given in the table below:
Shared I/O
Interface Type
Example Mode 1
Interface Type 2 * * * * * -
Example Mode 3 * * * * * GPIO7-0 IOB7-0
Host / GPIO2 Timer1 Timer2 UART1 UART2 GPIO0 GPIO1 FIFO RAM ADC DAC
* * * * * GPIO7-0 IOB7-0 active mode * *
* -
passive mode -
Note:
If the passive FIFO mode is used on the T7906E, the ADC and DAC interfaces can then not be used.
JTAG interface
For testing purposes a standard IEEE 1149.1 interface is provided. It supports the JTAG functions Bypass, Extest, Sample/Preload, All-Tristate and IDCode.
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Programming the T7906E
Programming the T7906E internal registers is done via a simple protocol over the IEEE1355 link or directly via the host interface. The link protocol consists of a command byte and, if necessary, one or more data bytes. All internal registers are 8-bit wide addressable. Two commands (read and write) suffice to access all registers of the T7906E. The T7906E provides registers and ports; a register contains exactly one byte (read / write), whereas a port (e.g. a FIFO interface) behaves like a FIFO, meaning that multiple data bytes can be read or written from/to the port. The ports of the T7906E such as the FIFO, UART, ADC and RAM interface are accessed by a read/write command to the corresponding port address. In the case of FIFO, Host, UART and memory interface, a packet oriented access is also possible (meaning transferring multiple data bytes with a single command). The read/write selection of a command is done by setting bit7 (msb) of the first byte to one (read) or zero (write).
Signal Description
This section describes the signals of the T7906E. Groups of signals represent busses where the highest number is the MSB.
Signal
Direction
Description
max. output load [mA]
Signal [pF]
HSEL*
I
when low, the external host selects the T7906E host interface host interface write/read signal if HWRnRD is high during HSEL* low, the host writes data to the address register or to the T7906E registers. if HWRnRD is low during HSEL* low, the host reads data from the address register or the T7906E registers. host interface data/address signal if HDATnADR is high during read, the host reads/writes data from/to the internal T7906E (data) registers. if HDATnADR is low during read, the host reads/writes address from/to the address register. T7906E data bus. This data lines will be used to access
HWRnRD
I
HDATnADR
I
HDATA(7:0)
I/O
the T7906E registers. HDATA(7:0) can also be used as GPIO(2), if Host interface is disabled.
3
50
HINTR* TMR1_CLK
O I
host interrupt request line timer1 clock (max. 12.5 MHz) timer1 expired. Asserted for one cycle
3
50
TMR1_EXP
O
if the value of counter1 is equal to the content of register TPERIOD1(3:0).
3
50
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T7906E
Signal Direction Description max. output load [mA] TMR2_CLK I timer2 clock (max. 12.5 MHz) timer2 expired. Asserted for one cycle TMR2_EXP. O if the value of counter2 is equal to the content of register TPERIOD2(3:0) RxD1 TxD1 LDI LSI LDO LSO DATA(15:0) GPIO(7:0) I O I I O O I/O I/O receive data to UART1 transmit data from UART1 Link Data Input Link Strobe Input Link Data Output Link Strobe Output common T7906E data bus General purpose input/output lines. Control bus. The T7906E controls the connected interface via these lines. The function of each control signal is described in a separate table. Test Reset. Resets the test state machine. Test Clock. Provides an asynchronous clock for JTAG boundary scan Test Mode Select. Used to control the test state machine. This input should be left unconnected or tied to ground during normal operation! Test Data Input. Provides serial data for the boundary scan logic Test Data Output. Serial scan output of the boundary scan path T7906E Reset. Sets the T7906E to a known state. This input must be asserted (low) at power-up. The minimum width of RESET low is 2 cycles when CLK is running External clock input to T7906E (max. 5 MHz) Output of internal PLL. Used to connect a network of external RC devices Power Supply Ground 3 50 12 12 3 3 25 25 25 25 3 50 3 50 Signal [pF]
IOB(27:0)
I/O
see note (1)
25
TRST* TCK
I I
TMS
I
TDI
I
TDO
O/Z
RESET*
I
CLK PLLOUT VCC GND
I O
Note:
1. IOB15-0, IOB21-18: 6 mA IOB17-16: 8mA IOB24-22: 3mA IOB27-25: input only
All inputs have an internal pull-up resistor, with the following exceptions, which have an internal pull-down resistor: LDI, LSI, TRST*, TMS.
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IOB Control Bus
Signal
The allocation of the I/O busses is shown in the table below:
Function RAM Interface Signal I/O O O O O O O O O O O O O O O O O O O I I I Function ADC/DAC/FIFO Interface ADC_ADDR[7:0] ADC_CS* ADC_R/C* DAC_WR* DAC_ADDR0 DAC_ADDR1 DAC_ADDR2 FIFO_TRM_EOP_ACK FIFO_RCV_PAR FIFO_RCV_EOP1 FIFO_RCV_EOP2 FIFO_RD* FIDO_WR* FIFO_EMPTY* FIFO_FULL* ADC:_RDY ADC_TRIG FIFO_TRM_EOP1 FIFO_TRM_EOP2 FIFO_RCV_EOP_ACK FIFO_TRM_PAR Signal I/O O O O O O O O O O O O B B B B I I I I I I Function GPIO GPIO1[7:0]
IOB[7:0] IOB8 IOB9 IOB10 IOB11 IOB12 IOB13 IOB14 IOB15 IOB16 IOB17 IOB18 IOB19 IOB20 IOB21 IOB22 IOB23 IOB24 IOB25 IOB26 IOB27
RAM_ADDR[7:0] RAM_ADDR8 RAM_ADDR9 RAM_ADDR10 RAM_ADDR11 RAM_ADDR12 RAM_ADDR13 RAM_ADDR14 RAM_ADDR15 RAM_WR* RAM_RD* RAM_CS0* RAM_CS1* RAM_CS2* RAM_CS3* RAM_TEST RAM_ TRM_RDY RAM_RCV_RDY RAM_BUS_REQ* RAM_START_TRM RAM_START_RCV
GPIO Signals
The pins GPIO0 to GPIO7 are either mapped on register GPIO0 (0x63 / 0x64) or miscellaneous I/O signals, depending on the register settings as shown in the table below:
Pin GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Mapped to RTS1*UART1 CTS1*UART1 EXT_IREQ0* EXT_IREQ1* TxD2UART2 RxD2UART2 RTS2*UART2 CTS2*UART2 I/O O I I I O I O I Register UART1_CTRL (0x59): D7 UART1_CTRL (0x59): D 7 IFCONF (0x01): D6 IFCONF (0x01): D 6 IFCONF (0x01): D7 IFCONF (0x01): D7 UART2_CTRL (0x72): D7 UART2_CTRL (0x72): D7
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T7906E
ELECTRICAL Specifications
This data is given for information only. For guaranteed values refer to Atmelk procurement specifications. Table 1. Absolute Maximum Ratings
Parameter Supply Voltage I/O Voltage Operating Temperature Range (Ambient) Junction Temperature Storage Temperature Range Thermal Resistance TA TJ Tstg Rthje Rthja Symbol VCC Value -0,5 to +7 -0,5 to Vcc+0,5 -55 to +125 Tj < TA+20 -65 to +150 1 35 Unit V V
C C C C/W
Stresses above those listed may cause permanent damage to the device.
DC Electrical Characteristics
Table 2. DC Characteristics Specified at VCC = + 5 V 10%
Parameter Operating Voltage Input HIGH Voltage (TTL) Input LOW Voltage (TTL) Output HIGH Voltage Output LOW Voltage Output Short circuit current Symbol VCC VIH VIL VOH VOL IOS 2,4 0,4 160 130 Min. 4,5 2,0 0,8 Max. 5,5 Unit V V V V V mA mA max. output current (1) max. output current (1) VOUT = VCC VOUT = GND Conditions
Note:
see also the signal description in section 4.
Power Consumption
Although specified for TTL outputs, all T7906E outputs are CMOS compatible and will drive VCC and GND assuming no DC loads. The max. power consumption figures (at 5,5V, -55xC) are:
Operating Mode at Reset in Idle operating
Symbol I I I
Max. 15 50 80
Unit mA mA mA
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PLL-Filter
The pin PLLOUT should be connected as shown below:
T7906E
PLLOUT R1 C1 * * * R1 = 249_ 5%, 1/4W C1 = 1nF, 5%, 200V C2 = 15nF, 5%, 200V C2
Power and Ground Guidelines
To achieve its fast cycle time, the T7906E is designed with high speed drivers on output pins. Large peak currents may pass through a circuit board's ground and power lines, especially when many output drivers are simultaneously charging or discharging their load capacitances. These transient currents can cause disturbances on the power and ground lines. To minimize these effects, the T7906E provides separate supply pins for its internal logic and for its external drivers. All GND pins should have a low impedance path to ground. A ground plane is required in T7906E systems to reduce this impedance, minimizing noise. The VCC pins should be bypassed to the ground plane using 8 high-frequency capacitors (0.1 mF ceramic). Keep each capacitor's lead and trace length to the pins as short as possible. This low inductive path provides the T7906E with the peak currents required when its output drivers switch. The capacitors' ground leads should also be short and connect directly to the ground plane. This provides a low impedance return path for the load capacitance of the T7906E output drivers. The following pins must have a capacitor: 1, 4, 16, 27, 56, 61, 88 and 99.
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T7906E
Timing Parameters
Clock
Description CLK period CLK width high CLK width low
Symbol tCLK tCLKH tCLKL
Min.
1)
Max.
1)
Unit ns ns ns
80 80
120 120
Note:
1) Nominal 5MHz
Reset
Description RESET* setup before CLK high RESET* low pulse width Output disable after CLK high
Symbol tRSTS tRSTW tOUTD
Min. 10 2*tCLK
Max.
Unit ns ns
38
ns
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Host write address
Description HSEL* active low pulse width HSEL* inactive high pulse width HWRnRD setup before HSEL* active low HDATnADR setup before HSEL* active low HWRnRD hold after HSEL* inactive high HDATnADR hold after HSEL* inactive high HDATA valid after HSEL active low and HWRnRD high HDATA hold after HSEL inactive high
Symbol tHSL tHSH tHWnRS tHWnRH tHWnRH tHDnAH tHDWV tHDWH
Min. 150 60 5 5 0 0
Max.
Unit ns ns ns ns ns ns
25 0
ns ns
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T7906E
Host write data
Description HSEL* active low pulse width HSEL* inactive high pulse width HWRnRD setup before HSEL* active low HDATnADR setup before HSEL* active low HWRnRD hold after HSEL* inactive high HDATnADR hold after HSEL* inactive high HDATA valid after HSEL active low and HWRnRD high HDATA hold after HSEL inactive high
Symbol tHSL tHSH tHWnRS tHWnRH tHWnRH tHDnAH tHDWV tHDWH
Min. 150 60 5 5 0 0
Max.
Unit ns ns ns ns ns ns
25 0
ns ns
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Host read address
Description HSEL* active low pulse width HSEL* inactive high pulse width HWRnRD setup before HSEL* active low HDATnADR setup before HSEL* active low HWRnRD hold after HSEL* inactive high HDATnADR hold after HSEL* inactive high HDATA enable after HSEL* active low and HWRnRD low HDATA valid after HSEL* active low and HWRnRD low HDATA hold after HSEL* inactive high
Symbol tHSL tHSH tHWnRS tHWnRH tHWnRH tHDnAH tHDE tHDV tHDH
Min. 150 60 5 5 0 0 4
Max.
Unit ns ns ns ns ns ns
18 125
ns ns ns
4
18
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T7906E
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T7906E
Host read data
Description HSEL* active low pulse width HSEL* inactive high pulse width HWRnRD setup before HSEL* active low HDATnADR setup before HSEL* active low HWRnRD hold after HSEL* inactive high HDATnADR hold after HSEL* inactive high HDATA enable after HSEL* active low and HWRnRD low HDATA valid after HSEL* active low and HWRnRD low HDATA hold after HSEL* inactive high
Symbol tHSL tHSH tHWnRS tHWnRH tHWnRH tHDnAH tHDE tHDV tHDH
Min. 150 60 5 5 0 0 4
Max.
Unit ns ns ns ns ns ns
18 125
ns ns ns
4
18
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RAM interface write
Description RAM I/F write access time CS0-3*, WR* active low pulse width Address ADDR0-15 valid before CS0*, WR* active low Address ADDR0-15 hold after CS0-3*, WR* inactive high DATA0-15 enable after CS0-3*, WR* active low DATA0-15 valid before CS0-3*, WR* inactive high DATA0-15 hold after CS0-3*, WR* inactive high
Symbol tRWA tRWL tRWAS tRWAH tRWDE tRWDV tRWDH
Min. 120 40+ws *40 38 38 0 32 20
1)
Max. 120+ws1)*40 42+ws *40 42 42 6
1)
Unit ns ns ns ns ns ns
26
ns
Note:
ws = wait states (0 - 7)
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RAM interface read
Description CS0-3*, WR*, RD* and ADDR valid active low pulse width CS0-3*, WR*, RD* and ADDR valid inactive high pulse width ADDRESS change2) DATA0-15 setup before CS0-3*, RD* high or new address on ADDR0-15 valid DATA hold after CS0-3*, RD* high or new address on ADDR0-15
Symbol tRRL tRRH tRRA tRDS tRDH
Min. 40+ws1)*40 38 40+ws1)*40 14 0
Max. 42+ws1)*40 40 42+ws1)*40
Unit ns ns ns ns
40
ns
Notes:
1. ws = wait states (0 - 7) 2. Internal clock runs at 25 MHz, ticlk = 40 ns
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RAM interface external bus request
Description CS0-3*, WR*, RD*, ADDR0-15 and DATA0-15 disable after BUS_REQ* active low CS0-3*, WR*, RD*, ADDR0-15 and DATA0-15 enable after BUS_REQ inactive high
Symbol tRBRS tRBRA
Min. 40
Max. 160
Unit ns
20
65
ns
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T7906E
RAM interface external control read
Description START_TRM high active pulse width START_TRM low inactive pulse width first read access (CS0-3* / RD* low active) after START_TRM high TRM_RDY (transmit ready) high active after the last read from memory time between the rising edge of TRM_RDY and the next start (rising edge from START_TRM) TRM_RDY hold after START_TRM high
Symbol tRETH tRETL tRETC tRETR tRETS tRETD
Min. 47 47 120
Max.
Unit ns ns
1)
ns
160
1)
ns
0 170
ns ns
Note:
1) depends on: - data bandwidth over the IEEE-1355 link - simultaneous read from the memory with wait states
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RAM interface external control write
Description START_RCV high active pulse width START_RCV low inactive pulse width first write access (CS0-3* / WR* low active) after START_RCV high RCV_RDY (receive ready) high inactive after the last write to memory time between the rising edge of RCV_RDY and the next start (rising edge from START_RCV) RCV_RDY hold after START_RCV high
Symbol tRERH tRERL tRERC tRERR tRERS tRERD
Min. 47 47 120
Max.
Unit ns ns
1)
ns
160
170
ns
0 170
ns ns
Note:
1) depends on - data bandwidth over the IEEE-1355 link - simultaneous write to the memory with wait states - internal write to fifo full
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T7906E
FIFO interface write
Description WR* active low pulse width WR* inactive high pulse width WR* active low after RCV_EOP_ACK high FIFO_FULL* setup before WR* high RCVEOP1, RCVEOP2 high after last write and WR* high RCV_EOP_ACK active high pulse width RCVEOP1, RCVEOP2 low after RCV_EOP_ACK high DATA0-7 enable after WR* low DATA0-7 valid before WR* high DATA0-7 hold after WR* high
Symbol tFWL tFWH tFWACK tFFS tFWEOP tFWEOPA tFWEOPH tFWDE tFWDV tFWDH
Min. 40+ws1)*40 38 120 8 40 49
Max. 42+ws1)*40 40
Unit ns ns ns ns
2)
ns ns
128 0 32 2 6
ns ns ns ns
Notes:
1. ws = wait states (0 - 7) 2. depends on: - data bandwidth over the IEEE-1355 link
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FIFO interface read
Description RD* active low pulse width RD* inactive high pulse width FIFO_EMPTY* setup before RD* high TRM_EOP_ACKnowledge active high after TRMEOP1, TRMEOP2 high AND FIFO_EMPTY active low TRMEOP1, TRMEOP2 hold after TRM_EOP_ACK high TRM_EOP_ACK hold after TRMEOP1, TRMEOP2 low DATA0-7 setup before RD* inactive high DATA0-7 hold after RD* inactive high
Symbol tFRL tFRH tFES tFREOPA tFREOPH tFRACKH tFRDV tFRDH
Min. 40+ws1)*4 0 38 8 160 0 122 9 0
Max. 42+ws1)*4 0 40
Unit ns ns ns
2)
ns ns
128
ns ns ns
Notes:
1. ws = wait states (0 - 7) 2. depends on: - data bandwidth over the IEEE-1355 link
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ADC interface
Description ADC_CS* low pulse width ADC_RDY high pulse width ADC_RDY high to ADC_R/C* high ADC_R/C* setup before ADC_CS* low ADC_TRIG high pulse width ADC_TRIG high to ADC_CS* low DATA 0-15 setup to ADC_CS* high DATA 0-15 hold after ADC_CS* high
Symbol tADCCS tADCRDY tADCR tADCS tADCTRIG tADCTCS tADCDS tADCDH
Min. 40+ws*40 45 200 40+ws*40 45 200+ws*40 19 0
Max. 42+ws*40
Unit ns ns ns
42+ws*40
ns ns ns ns ns
Note:
ws = wait states (0 to 15)
DAC interface
Description DAC_ADDR 0-2 and DATA 0-15 setup before DAC_WR* low DAC_WR* low pulse width DATA 0-15 hold after DAC_WR* high
Symbol tDACS tDACWR tDACH
Min. 40+ws*40 40+ws*40 38
Max. 42+ws*40 42+ws*40 42
Unit ns ns ns
Note:
ws = wait states (0 to 15)
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Timer
Description TMRx_CLK period TMRx_CLK width high TMRx_CLK width low TMRx_EXP low / high after TMRx_CLK high
Symbol tTCLK tTCLKH tTCLKL tTEXP
Min. 80 35 35 9
Max.
Unit ns
45 45 24
ns ns ns
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T7906E
External Interrupt
Description EXT_IREQx low pulse width
Symbol tEXINT
Min. 10
Max.
Unit ns
26
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Links
Description Bit Period LDOx, LSOx output skew
1)
Symbol tLBITP tLOUTS tLDSI
Min. 4
Max.
Unit ns
0.5 1
ns ns
Data/Strobe edge separation
Note:
1) Output skew includes jitter
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Rev. A - 27-Aug.-01
T7906E
Test Port (JTAG)
Description TCK period TCK width high TCK width low TMS, TDI setup before TCK high TMS, TDI hold after TCK high TDO delay after TCK low SMCS Inputs setup before TCK high SMCS Inputs hold after TCK high SMCS Outputs delay after TCK low
Symbol tTCK tTCKH tTCKL tTIS tTIH tTDO tSYSS tSYSM tSYSO
Min. 100 40 40 8 8
Max.
Unit ns ns ns ns
17 8 8 27 ns ns ns
28
Rev. A - 27-Aug.-01
Test Port Reset
Description TDO disable after TRST* active low TRST* pulse width
Symbol tTDOZ tTRST
Min.
Max. 5
Unit ns ns
2 * tTCK
29
T7906E
Rev. A - 27-Aug.-01
T7906E
Mechanical Data
Package Dimensions
Figure 3. 100-Pin Ceramic Quad Flat Pack (MQFPF)
MILLIMETERS Symbol MIN A C D D1 E E1 e f A1 A2 L N1, N2 2.21 0.15 3 1.8 18.8 31.8 18.8 0.635 typ 0.254 ref 1.83 0.203 ref 6.5 25 MAX 2.67 0.2 32.8 19.3 32.8 19.3 0.025 typ 0.010 ref 2.24 0.008 ref 6.75 MIN
INCHES MAX 0.105 0.008 1.291 0.76 1.45 0.76 0.635 typ 0.254 ref 0.088 0.203 ref 0.266 25
0.087 0.006 1.252 0.74 1.252 0.74 e f 0.072 A2 0.256
30
Rev. A - 27-Aug.-01
Pin Assignment
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name VCC GND GND VCC LD0 LS0 LDI LSI GND TCK TMS TDI TRST* TD0 GND VCC IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 IOB8 IOB9 VCC GND IOB10 IOB11 IOB12 IOB13 IOB14 IOB15
The table below lists the pins and their function.
Pin Number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name IOB16 IOB17 IOB18 IOB19 IOB20 IOB21 IOB22 IOB23 IOB24 IOB25 IOB26 IOB27 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 VCC GND DATA9 DATA10 DATA11 VCC GND DATA12 DATA13 DATA14 DATA15 GPIO0 GPIO1 Pin Number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 TMR1_CLK TMR2_CLK RxD1 TMR1_EXP TMR2_EXP TxD1 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 VCC GND HDATA7 HDATNADR HSEL* HWRNRD HINTR* RESET* CLK GND GND VCC PLLOUT
31
T7906E
Rev. A - 27-Aug.-01
T7906E
Glossary
BSDLBoundary Scan Description Language CPU Central Processing Unit DPRAMDual-Port RAM DSM Ds-link Macrocell DSP Digital Signal Processor EOP End Of Packet GPIO General Purpose Input/Output FIFO First In, First Out HOCI Host Control Interface HW Hardware
JTAG Joint Test Action Group LSB Least Significant Bit (or Byte) MSB Most Significant Bit (or Byte) PLL Phase Locked Loop SIC Simple Interprocessor Communication
SMCSScalable Multichannel Communication Subsystem UARTUniversal Asynchronous Receiver Transmitter
Ordering Information
Part-Number T7906EKT-E T7906EKT T7906EKT/SC T7906EKT/SB T7906EKT/883* T7906EKST/883* T7906EKTMQ T7906EKTSV T7906EDD-E T7906EDDMQ T7906EDDSV
Temperature Range +25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C +25C -55 to +125C -55 to +125C
Package MQFPF100 MQFPF100 MQFPF100 MQFPF100 MQFPF100 MQFPF100 MQFPF100 MQFPF100 Die Die Die
Quality Engineering Samples MIL SCC B SCC C MIL 883 B MIL 883 S QML Q QML V Engineering Samples QML Q QML V
Note:
(*)contact factory.
32
Rev. A - 27-Aug.-01
Appendix
-- BSDL for SMCSlite -- Uses HP's BSDL format and compiles correctly using HP's -- parser or compiler of JTAG Technologies -- Author Paul Rastetter, Astrium GmbH -- Tel.: +49-89-607-25015, Fax: +49-89-607-28964 -- e-mail: paul.rastetter@astrium-space.com -- date: 24-11-00
entity SMCSLITE is
generic (PHYSICAL_PIN_MAP : string := "UNDEFINED"); PORT (BYPPLL : IN bit; CLK : IN bit; HDATNADR : IN bit; HWRNRD : IN bit; LDI : IN bit; LSI : IN bit; NHSEL : IN bit; NRESET : IN bit; TRST : IN bit; RXD : IN bit; TCK : IN bit; TDI : IN bit; TMR1_CLK : IN bit; TMR2_CLK : IN bit; TMS : IN bit; iob25 : IN bit; iob26 : IN bit; iob27 : IN bit; LDO : OUT bit; LSO : OUT bit; NHINTR : OUT bit; TDO : OUT bit; TMR1_EXP : OUT bit; TMR2_EXP : OUT bit; TXD : OUT bit; IOB8 : OUT bit; IOB9 : OUT bit; iob10 : OUT bit; iob11 : OUT bit; iob12 : OUT bit; iob13 : OUT bit; iob14 : OUT bit; iob15 : OUT bit; iob16 : OUT bit; iob17 : OUT bit;
33
T7906E
Rev. A - 27-Aug.-01
T7906E
DATA : INOUT bit_vector(0 TO 15); GPIO : INOUT bit_vector(0 TO 7); HDATA : INOUT bit_vector(0 TO 7); IOB0 : INOUT bit; iob1 : INOUT bit; iob2 : INOUT bit; iob3 : INOUT bit; iob4 : INOUT bit; iob5 : INOUT bit; iob6 : INOUT bit; iob7 : INOUT bit; iob18 : INOUT bit; iob19 : INOUT bit; iob20 : INOUT bit; iob21 : INOUT bit; iob22 : INOUT bit; iob23 : INOUT bit; iob24 : INOUT bit; VDD : linkage bit_vector(0 to 7); GND : linkage bit_vector(0 to 7); NC : linkage bit_vector(0 to 1) );
use STD_1149_1_1990.all; attribute PIN_MAP of SMCSLITE : entity is PHYSICAL_PIN_MAP; constant MCQFP_PACKAGE : PIN_MAP_STRING := "LDO: 5," & "LSO: 6," & "LDI: 7," & "LSI: 8," & "TCK: 10," & "TMS: 11," & "TDI: 12," & "TRST: 13," & "TDO: 14," & "IOB0: 17," & "IOB1: 18," & "IOB2: 19," & "IOB3: 20," & "IOB4: 21," & "IOB5: 22," & "IOB6: 23," & "IOB7: 24," & "IOB8: 25," & "IOB9: 26," & "IOB10: 29," & "IOB11: 30," & "IOB12: 31," &
34
Rev. A - 27-Aug.-01
"IOB13: 32," & "IOB14: 33," & "IOB15: 34," & "IOB16: 35," & "IOB17: 36," & "IOB18: 37," & "IOB19: 38," & "IOB20: 39," & "IOB21: 40," & "IOB22: 41," & "IOB23: 42," & "IOB24: 43," & "IOB25: 44," & "IOB26: 45," & "IOB27: 46," & "DATA: (47,48,49,50,51,52,53,54,55,58,59,60,63,64,65,66)," & "GPIO: (67,68,69,70,71,72,73,74)," & "TMR1_CLK:75," & "TMR2_CLK:76," & "RXD: 77," & "TMR1_EXP:78," & "TMR2_EXP:79," & "TXD: 80," & "HDATA: (81,82,83,84,85,86,87,90)," & "HDATNADR:91," & "NHSEL: 92," & "HWRNRD: 93," & "NHINTR: 94," & "NRESET: 95," & "CLK: 96," & "BYPPLL: 97," & "VDD: (1,4,16,27,56,61,88,99)," & "GND: (2,3,15,28,57,62,89,98)," & "NC: (9,100)"; -- for completeness: scan_en, pllout,
attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of SMCSLITE : entity is 3;
attribute INSTRUCTION_OPCODE of SMCSLITE : entity is "BYPASS (111,110,101,100)," & "EXTEST (000)," & "SAMPLE (001)," &
35
T7906E
Rev. A - 27-Aug.-01
T7906E
"IDCODE (010)," & "HIGHZ (011)";
attribute INSTRUCTION_CAPTURE of SMCSLITE : entity is "101";
attribute INSTRUCTION_DISABLE of SMCSLITE : entity is "HIGHZ";
attribute IDCODE_REGISTER of SMCSLITE : entity is "0001" & -- Version "0101001101001100" & -- Part number 534C = SL "00001011000" & -- ID of manufacturer; MATRA MHS is 58 hex "1"; -- required by IEEE Std 1149.1-1990 (LSB)
attribute REGISTER_ACCESS of SMCSLITE : entity is "BSREG (EXTEST, SAMPLE)," & "BOUNDARY (EXTEST, SAMPLE),"& -- "IDREG (IDCODE)," & "BYPASS (BYPASS, HIGHZ)"; -- "BPREG (BYPASS, HIGHZ)";
--
attribute BOUNDARY_CELLS of SMCSLITE : entity is "BC_1"; -- BC_1: output, control; BC_1: input;
attribute BOUNDARY_LENGTH of SMCSLITE : entity is 155;
attribute BOUNDARY_REGISTER of SMCSLITE : entity is
-- num cell port
" " " " " " " " " " " "
func safe [ccell disval rslt] 0 (BC_1, LSI, input, X)," & 1 (BC_1, LDI, input, X)," & 2 (BC_1, LSO, output2, X)," & 3 (BC_1, LDO, output2, X)," & 4 (BC_1, BYPPLL, input, X)," & 5 (BC_1, CLK, input, X)," & 6 (BC_1, NRESET, input, X)," & 7 (BC_1, NHINTR, output2, X)," & -- output2 for internal tristate 8 (BC_1, HWRNRD, input, X)," & 9 (BC_1, NHSEL, input, X)," & 10 (BC_1, HDATNADR, input, X)," & 11 (BC_1, * , control, 0)," & -- HOCI Data Output Enable7
36
Rev. A - 27-Aug.-01
" 12 (BC_1, HDATA(7), output3, X, 11, " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
0,
Z)," &
(BC_1, HDATA(7), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable6 (BC_1, HDATA(6), output3, X, 14, 0, Z)," & (BC_1, HDATA(6), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable5 (BC_1, HDATA(5), output3, X, 17, 0, Z)," & (BC_1, HDATA(5), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable4 (BC_1, HDATA(4), output3, X, 20, 0, Z)," & (BC_1, HDATA(4), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable3 (BC_1, HDATA(3), output3, X, 23, 0, Z)," & (BC_1, HDATA(3), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable2 (BC_1, HDATA(2), output3, X, 26, 0, Z)," & (BC_1, HDATA(2), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable1 (BC_1, HDATA(1), output3, X, 29, 0, Z)," & (BC_1, HDATA(1), input, X)," & (BC_1, * , control, 0)," & -- HOCI Data Output Enable0 (BC_1, HDATA(0), output3, X, 32, 0, Z)," & (BC_1, HDATA(0), input, X)," & (BC_1, TXD, output2, X)," & -- output2 for internal tristate (BC_1, TMR2_EXP, output2, X)," & -- output2 for internal tristate (BC_1, TMR1_EXP, output2, X)," & -- output2 for internal tristate (BC_1, RXD, input, X)," & (BC_1, TMR2_CLK, input, X)," & (BC_1, TMR1_CLK, input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable7 (BC_1, GPIO(7), output3, X, 41, 0, Z)," & (BC_1, GPIO(7), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable6 (BC_1, GPIO(6), output3, X, 44, 0, Z)," & (BC_1, GPIO(6), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable5 (BC_1, GPIO(5), output3, X, 47, 0, Z)," & (BC_1, GPIO(5), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable4 (BC_1, GPIO(4), output3, X, 50, 0, Z)," & (BC_1, GPIO(4), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable3 (BC_1, GPIO(3), output3, X, 53, 0, Z)," & (BC_1, GPIO(3), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable2 (BC_1, GPIO(2), output3, X, 56, 0, Z)," & (BC_1, GPIO(2), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable1 (BC_1, GPIO(1), output3, X, 59, 0, Z)," & (BC_1, GPIO(1), input, X)," & (BC_1, * , control, 0)," & -- GPIO Output Enable0
37
T7906E
Rev. A - 27-Aug.-01
T7906E
" " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 (BC_1, GPIO(0), output3, X, 62, 0, Z)," & (BC_1, GPIO(0), input, X)," & (BC_1, * , control, 0)," & -- DATA Output Enable (BC_1, DATA(15), output3, X, 65, 0, Z)," & (BC_1, DATA(15), input, X)," & (BC_1, DATA(14), output3, X, 65, 0, Z)," & (BC_1, DATA(14), input, X)," & (BC_1, DATA(13), output3, X, 65, 0, Z)," & (BC_1, DATA(13), input, X)," & (BC_1, DATA(12), output3, X, 65, 0, Z)," & (BC_1, DATA(12), input, X)," & (BC_1, DATA(11), output3, X, 65, 0, Z)," & (BC_1, DATA(11), input, X)," & (BC_1, DATA(10), output3, X, 65, 0, Z)," & (BC_1, DATA(10), input, X)," & (BC_1, DATA(9), output3, X, 65, 0, Z)," & (BC_1, DATA(9), input, X)," & (BC_1, DATA(8), output3, X, 65, 0, Z)," &
81 (BC_1, DATA(8), input, X)," & 82 (BC_1, DATA(7), output3, X, 65, 0, Z)," & 83 (BC_1, DATA(7), input, X)," & 84 (BC_1, DATA(6), output3, X, 65, 0, Z)," & 85 (BC_1, DATA(6), input, X)," & 86 (BC_1, DATA(5), output3, X, 65, 0, Z)," & 87 (BC_1, DATA(5), input, X)," & 88 (BC_1, DATA(4), output3, X, 65, 0, Z)," & 89 (BC_1, DATA(4), input, X)," & 90 (BC_1, DATA(3), output3, X, 65, 0, Z)," & 91 (BC_1, DATA(3), input, X)," & 92 (BC_1, DATA(2), output3, X, 65, 0, Z)," & 93 (BC_1, DATA(2), input, X)," & 94 (BC_1, DATA(1), output3, X, 65, 0, Z)," & 95 (BC_1, DATA(1), input, X)," & 96 (BC_1, DATA(0), output3, X, 65, 0, Z)," & 97 (BC_1, DATA(0), input, X)," & 98 (BC_1, IOB27, input, X)," & 99 (BC_1, IOB26, input, X)," & 100 (BC_1, IOB25, input, X)," & 101 (BC_1, * , control, 0)," & -- IOB Output Enable 102 (BC_1, IOB24, output3, X, 101, 0, Z)," & 103 (BC_1, IOB24, input, X)," & 104 (BC_1, IOB23, output3, X, 101, 0, Z)," & 105 (BC_1, IOB23, input, X)," & 106 (BC_1, IOB22, output3, X, 101, 0, Z)," & 107 (BC_1, IOB22, input, X)," & 108 (BC_1, * , control, 0)," & -- IOB Output Enable 109 (BC_1, IOB21, output3, X, 108, 0, Z)," & 110 (BC_1, IOB21, input, X)," & 111 (BC_1, * , control, 0)," & -- IOB Output Enable 112 (BC_1, IOB20, output3, X, 111, 0, Z)," & 113 (BC_1, IOB20, input, X)," &
38
Rev. A - 27-Aug.-01
" 114 (BC_1, * , control, 0)," & -- IOB Output Enable " 115 (BC_1, IOB19, output3, X, 114, 0, Z)," & " 116 (BC_1, IOB19, input, X)," & " 117 (BC_1, * , control, 0)," & -- IOB Output Enable " 118 (BC_1, IOB18, output3, X, 117, 0, Z)," & " 119 (BC_1, IOB18, input, X)," & " 120 (BC_1, * , control, 0)," & -- IOB Output Enable " 121 (BC_1, IOB17, output3, X, 120, 0, Z)," & " 122 (BC_1, IOB16, output3, X, 120, 0, Z)," & " 123 (BC_1, IOB15, output3, X, 120, 0, Z)," & " 124 (BC_1, IOB14, output3, X, 120, 0, Z)," & " 125 (BC_1, IOB13, output3, X, 120, 0, Z)," & " 126 (BC_1, IOB12, output3, X, 120, 0, Z)," & " 127 (BC_1, IOB11, output3, X, 120, 0, Z)," & " 128 (BC_1, IOB10, output3, X, 120, 0, Z)," & " 129 (BC_1, IOB9, output3, X, 120, 0, Z)," & " 130 (BC_1, IOB8, output3, X, 120, 0, Z)," & " 131 (BC_1, * , control, 0)," & -- IOB Output Enable " 132 (BC_1, IOB7, output3, X, 131, 0, Z)," & " 133 (BC_1, IOB7, input, X)," & " 134 (BC_1, * , control, 0)," & -- IOB Output Enable " 135 (BC_1, IOB6, output3, X, 134, 0, Z)," & " 136 (BC_1, IOB6, input, X)," & " 137 (BC_1, * , control, 0)," & -- IOB Output Enable " 138 (BC_1, IOB5, output3, X, 137, 0, Z)," & " 139 (BC_1, IOB5, input, X)," & " 140 (BC_1, * , control, 0)," & -- IOB Output Enable " 141 (BC_1, IOB4, output3, X, 140, 0, Z)," & " 142 (BC_1, IOB4, input, X)," & " 143 (BC_1, * , control, 0)," & -- IOB Output Enable " 144 (BC_1, IOB3, output3, X, 143, 0, Z)," & " 145 (BC_1, IOB3, input, X)," & " 146 (BC_1, * , control, 0)," & -- IOB Output Enable " 147 (BC_1, IOB2, output3, X, 146, 0, Z)," & " 148 (BC_1, IOB2, input, X)," & " 149 (BC_1, * , control, 0)," & -- IOB Output Enable " 150 (BC_1, IOB1, output3, X, 149, 0, Z)," & " 151 (BC_1, IOB1, input, X)," & " 152 (BC_1, * , control, 0)," & -- IOB Output Enable " 153 (BC_1, IOB0, output3, X, 152, 0, Z)," & " 154 (BC_1, IOB0, input, X)"; end SMCSLITE;
39
T7906E
Rev. A - 27-Aug.-01
T7906E
40
Rev. A - 27-Aug.-01
41
T7906E
Rev. A - 27-Aug.-01
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